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Chapter 4
4-1 DISABLING INTERRUPTS
When setting OS_CFG_ISR_POST_DEFERRED_EN to 0, μC/OS-III will disable interrupts before
entering a critical section and re-enable them when leaving the critical section.
OS_CRITICAL_ENTER() invokes the μC/CPU macro CPU_CRITICAL_ENTER() that, in turn,
calls CPU_SR_Save() . CPU_SR_Save() is a function typically written in assembly language
that saves the current interrupt disable status and then disables interrupts. The saved
interrupt disable status is returned to the caller and in fact, it is stored onto the caller’s stack
in a variable called “ cpu_sr ”.
OS_CRITICAL_EXIT() and OS_CRITICAL_EXIT_NO_SCHED() both invoke the μC/CPU
macro CPU_CRITICAL_EXIT() , which maps to CPU_SR_Restore() . CPU_SR_Restore() is
passed the value of the saved “ cpu_sr ” variable to re-establish interrupts the way they were
prior to calling OS_CRITICAL_ENTER() .
The typical code for the macros is shown in Listing 4-1.
#define
#define
#define
OS_CRITICAL_ENTER()
OS_CRITICAL_EXIT()
OS_CRITICAL_EXIT_NO_SCHED()
{ CPU_CRITICAL_ENTER(); }
{ CPU_CRITICAL_EXIT(); }
{ CPU_CRITICAL_EXIT(); }
Listing 4-1 Critical section code – Disabling interrupts
4-1-1 MEASURING INTERRUPT DISABLE TIME
μC/CPU provides facilities to measure the amount of time interrupts are disabled. This is
done by setting the configuration constant CPU_CFG_TIME_MEAS_INT_DIS_EN to 1 in
CPU_CFG.H .
The measurement is started each time interrupts are disabled and ends when interrupts are
re-enabled. The measurement keeps track of two values: a global interrupt disable time, and
an interrupt disable time for each task. Therefore, it is possible to know how long a task
disables interrupts, enabling the user to better optimize their code.
The per-task interrupt disable time is saved in the task’s OS_TCB during a context switch (see
OSTaskSwHook() in OS_CPU_C.C and described in Chapter 8, “Context Switching” on
page 147).
70
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